Method for covering a first layer or layer sequence situated...

Details Method for covering a first layer or layer sequence situated... Method for covering a first layer or layer sequence situated...

H - Electricity

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356/148

H01L 21/302 (2006.01) C23C 14/34 (2006.01) H01L 21/033 (2006.01) H01L 21/311 (2006.01) H01L 21/316 (2006.01) H01L 21/3213 (2006.01)

Patent

CA 1094228

ABSTRACT OF THE DISCLOSURE A method is disclosed for eliminating under-etchings. In a substrate having a lower silicon dioxide layer thereon, a polysilicon layer on the silicon dioxide layer, and an upper silicon dioxide layer on the polysilicon layer, an etched window provided in the layers has first under-etchings formed at an edge of the lower silicon dioxide layer adja- cent the substrate and a second under-etching formed at an edge of the polysilicon layer. A sputtering source is provided with a given target voltage. A grid potential is applied to the substrate wherein the grid potential is between one-tenth and one-third of the target voltage. A layer is then sputtered on in the etching window for filling in the first under- etching by re-emission from the surface of the substrate and for sloping the edge of the polysilicon layer at the second under-etching. An over- hanging portion of the upper silicon dioxide layer is also removed at the second under-etching by re-emission during the sputtering on.

296570

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