Method for fabricating minute openings in integrated circuits

Details Method for fabricating minute openings in integrated circuits Method for fabricating minute openings in integrated circuits

G - Physics

03

G

96/215

G03G 13/26 (2006.01) H01L 21/00 (2006.01) H01L 21/308 (2006.01)

Patent

CA 1048331

A METHOD FOR FABRICATING MINUTE OPENINGS IN INTEGRATED CIRCUITS Abstract of Disclosure A method in the fabrication of integrated circuits for forming small openings through electrically insula- tive passivating layers on semiconductor surfaces. First and second layers of different insulative material are formed on the semiconductor surface. Then, a first slot extending through the second or top layer is formed by chemical etching through an etch-resistant mask with an etchant which selectively etches the material in the top layer. The top layer is then covered with a photoresist mask having a second slot which crosses the first slot, and the structure is subjected to chemical etching through the photoresist mask with an etchant that selec- tively etches the material in the first or bottom layer to, thereby, form a small opening through this bottom layer which is defined by the intersecting portions of the first and second slots.

213610

Affiliated with

Also associated with

Rating

Method for fabricating minute openings in integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating minute openings in integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating minute openings in integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1131367