Semiconductor integrated circuits and manufacturing process...

Details Semiconductor integrated circuits and manufacturing process... Semiconductor integrated circuits and manufacturing process...

H - Electricity

01

L

356/132

H01L 21/762 (2006.01) H01L 21/027 (2006.01) H01L 21/768 (2006.01) H01L 27/04 (2006.01)

Patent

CA 1175956

ABSTRACT OF THE DISCLOSURE A semiconductor integrated circuit in which layers such as an field isolation region, a gate electrode, inter- layer insulating films and interconnection lines are formed by the combined use of a lift-off process and an ECR plasma deposition process. According to the present invention, even if vertical dimensions of patterns of the respective layers are large as compared with their lateral dimensions, the upper surfaces of the respective layers can be planarized, permitting the fabrication of an LSI of high packing density, high operating speed and high reliability which is free from shorting and breakage of the interconnection lines.

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