Fast c-mos adder

G - Physics – 06 – F

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354/214

G06F 7/50 (2006.01) G06F 7/52 (2006.01)

Patent

CA 1282176

Abstract An integrated circuit implementation of a carry propagating adder and related function incorporates elementary carry-propagating adder cells having two circuit branches, a first of which as an inverter followed by a transfer gate activated when two operands have opposite logic levels, in which case it transfers a complemented carry input to a carry output. The second branch incorporates a 4-transistor series circuit, made up of two P-MOS and two N-MOS transistors, which generates a complemented carry output when the two operands have the same logic level.

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