Firmware state machine

Details Firmware state machine Firmware state machine

H - Electricity

04

Q

379/2, 354/222

H04Q 3/545 (2006.01) G06F 9/00 (2006.01) G06F 13/12 (2006.01)

Patent

CA 1287932

ABSTRACT A firmware state apparatus for controlling data transfer on multiple independent data lines between a telephone communications sytem and computer system. At least one processor having a program counter is employed for control of data transfer. A processor memory is associated with the processor and has a plurality of firmware instructions divided into groups based upon the number of predefined states which are required for performing data transfer. Certain groups of instructions include test instructions for evaluating conditions related to the line to control sequencing to a next one of the predefined states. A shared memory has a plurality of locations for line table information for at least one line with at least one location containing a program counter address specifying a starting instruction of a corresponding one of the group of instructions to be executed by the processor. The processor, in response to the group of instructions, performs a designated operation for the line and in particular in response to the test instruction loads a new value corresponding to the starting instruction of the group of instructions of the next state.

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