Data encoding/decoding circuit

Details Data encoding/decoding circuit Data encoding/decoding circuit

H - Electricity

04

L

354/67, 340/70

H04L 9/18 (2006.01)

Patent

CA 1256577

Abstract of the Disclosure In a data encoding/decoding circuit, a data encoding circuit includes a first clock, a first time setting circuit, a first random number generator, and a converter for receiving transmission data and converting the transmission data into output data with frame sync signals. A data decoding circuit includes a second clock, a second time-setting circuit, a frame sync extracting circuit, a time correction circuit for correcting the time of the second clock, a second random number generator, and an inverter for inverting output data from the frame sync extracting circuit with a random number from the second random number generator and outputting the inverted data as decoded data.

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