Central processor

Details Central processor Central processor

G - Physics

06

F

354/230.87

G06F 9/38 (2006.01) G06F 7/00 (2006.01) G06F 9/34 (2006.01) G06F 12/08 (2006.01) G06F 13/00 (2006.01)

Patent

CA 1200318

A B S T R A C T A central processor for a general-purpose digital data processing system. The processor has a pair of caches, an operand cache for operands and an instruction cache for instructions, as well as a plurality of execution units, where each execution unit executes a different set of instructions of the instruction repertoire of the central processor. An instruction fetch unit fetches instructions from the instruction cache and stores them in an instruction of a given program stack. The central pipeline unit which has five stages obtains instructions in program order from the instruction stack of the instruction fetch unit. In the first stage of the central pipeline unit, the instruction is de- coded; in the second, the address preparation of an operand whose address is included in the instruction is initiated; in the third cycle, the address preparation is completed and the operand cache is accessed; in the fourth cycle, the operand is selected from the operand cache; and, in the fifth cycle, the instruction and operand are transmitted to the one of the plurality of execution units capable of executing the instruction of the program in execution. The results of the execution of each instruction by each execution unit are stored in a results stack associated therewith. A collector unit causes the results of the execution of the instructions to be stored in a master safe store register in program order, which is determined by the order of issuance of the instructions by the central pipeline unit. The collector also issues write commands to store results of the execution of instructions into the operand cache.

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