Integrated circuit architecture and fabrication method therefor

Details Integrated circuit architecture and fabrication method therefor Integrated circuit architecture and fabrication method therefor

H - Electricity

01

L

356/30

H01L 27/02 (2006.01) H01L 21/70 (2006.01) H01L 23/528 (2006.01) H01L 27/118 (2006.01)

Patent

CA 1231465

ABSTRACT A new ensemble of logic elements organized in an array and a method of forming the same is described wherein the architecture includes a main field of transis- tor elements formed on a substrate material. A group of load transistors and an array of logic gates are formed on the substrate and are located within the main field of transistors, At least one routing channel is provided in the main field, and an input/output structure is located on the substrate. A region of flip-flop elements, also located within the main field, may be provided. Prefer- ably, a plurality of such groups, arrays and regions are formed in parallel strips extending across the main field, and a perpendicular bussing channel also extends across the field to divide the main field into component arrays. The logic gates may be configurable structures or dedi- cated inverters, and a plurality of input/output structures may be employed. The method includes the electrical interconnection of these elements into logic terms to form an integrated circuit.

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