Microprocessor having separate instruction and data interfaces

Details Microprocessor having separate instruction and data interfaces Microprocessor having separate instruction and data interfaces

G - Physics

06

F

354/241

G06F 12/08 (2006.01)

Patent

CA 1283222

ABSTRACT A microprocessor architecture is disclosed having separate very high speed instruction and data interface circutry for coupling via respective separate very high speed instruction and data interface buses to respective external instruction cache and data cache circuitry. The microprocessor is comprised of an instruction interface, a data interface, and an execution unit. The instruction interface controls communications with the external instruction cache and coupled the instructions from the instruction cache to the micro- processor at very high speed. The data interface controls communications with the external data cache and communicates data bi-directionally at very high speed between the data cache and the microprocessor. The execution unit selectively processes the data received via the data interface from the data cache responsive to the execution unit decoding and executing a respective one of the instructions received via the instruction interface from the instruction cache. In one embodiment, the external instruction cache is comprised of a program counter and addressable memory for outputting stored instructions responsive to its program counter and to an instruction cache advance signal output from the instruc- tion interface. An address generator in the instruction interface selectively outputs an initial instruction address for storage in the instruction cache program counter resonsive to a context switch or branch, such that the instruction interface repetitively couples a plurality of instructions from the instruction cache to the microprocessor responsive to the cache advance signal, independent of and without the need for any intermediate or further address output from the instruc- tion interface to the instruction cache except upon the occurrence of another context switch or branch.

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