G - Physics – 06 – F
Patent
G - Physics
06
F
354/231
G06F 1/04 (2006.01) G06F 1/10 (2006.01)
Patent
CA 1214883
ABSTRACT OF THE DISCLOSURE A digital computer has a clock signal source and a plurality of logic circuits each having a clock input. A delay circuit is associated with each clock input and is interposed between the clock source and the clock input. The delay circuits are under the control of a microprosessor to vary the amount of delay which is interposed in the clock signal by the delay circuits. Each delay circuit has a minimum delay point where the clock signal arrives at the associat- ed clock input early in time, and a maximum delay point where the clock signal arrives at the clock input late in time. In a first searching mode, the micro- processor starts with a selected clock input and associated delay circuit and sets the delay circuit to an initial clocking point intermediate the minimum and maximum delay points. The microprocessor then successively increments the de- lay period interposed by the delay circuit to cause the clock pulse to arrive later and later in time at the clock input until the associated logic circuit fails, thus indicating the late clocking failure limit. In the second searching mode, the microprocessor starts at the late clocking failure limit and succes- sively decrements the delay period interposed by the delay circuit to cause the clock signal to arrive earlier and earlier in time until the logic circuit fails again, thus indicating the early clocking failure limit. The early and late clocking failure limits, define a clocking window for the logic circuit. The microprocessor sets the delay circuit to the mid-point of the clocking window which is the optimal clocking point for the particular clock input. The micro- processor repeats this procedure for each delay circuit and associated clock input.
458946
Control Data Corporation
Smart & Biggar
LandOfFree
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