Phase tolerant bit synchronizer for digital signals

Details Phase tolerant bit synchronizer for digital signals Phase tolerant bit synchronizer for digital signals

H - Electricity

04

L

340/205, 328/87

H04L 7/00 (2006.01) H03L 7/085 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1175930

PHASE TOLERANT BIT SYNCHRONIZER FOR DIGITAL SIGNALS Abstract A bit synchronizer for digital data signals capable of tracking phase errors of up to ? 180° without loss of lock. An input data signal is squared and then applied to a pair of D-type flip-flops. The flip-flops are alternately driven by a clock signal generated by a voltage controlled oscillator in a phase-locked loop. me flip-flops cause the input data to be shifted 0° and 180°, respectively, with reference to the clock signal. The flip-flops are cross- coupled to a pair of exclusive-OR gates, in a manner such that as the phase error between the input signal and the clock signal increases or decreases, the pulse width out of one gate varies proportionately while the output of the other gate is a pulse which is always one-half the clock signal period. The phase relationship of the pulses out of the gates switch 180° as the phase error traverses the 0° point. me outputs of the gates are summed to provide a measure of the phase error between the clock signal and the input signal and to produce a net control voltage representative thereof. me control voltage is applied to the oscillator to cause the frequency and phase of the clock signal generated thereby to be synchronous with that of the input signal. In the absence of bit transitions, the phase-locked loop is biased to seek the tuned bit rate. The described arrangement permits tracking phase errors over a ? 180° range without loss of synchronization. -16-

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