Programmable clock

G - Physics – 05 – B

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342/11

G05B 19/042 (2006.01) G04G 15/00 (2006.01) G06F 1/14 (2006.01)

Patent

CA 1233897

ABSTRACT A user-programmable clock is provided for executing events defined by functions executed at a particular time and selected zones and for selected schedules. The clock includes an event memory for receiving zone and schedule data from a keyboard by way of a processor wherein the event memory is segregated into first, second and third tiers of event data. The processor of the clock is responsive to the keyboard for routing zone and schedule data entered from the keyboard to one of the three tiers of the event memory. The first tier of the event memory includes a plurality of locations wherein each location corresponds to an increment of time. Means are provided for selecting data stored in the first tier of the event memory at address locations corresponding to time data received from a timing mechanism. Means are also provided for selecting the appropriate data stored in the second and third tiers. Means are provided for combining the data selected from the first, second and third tiers and executing a function in response to the zone and schedule information contained in the combined data in order to execute the function at the time indicated by the time data and in the zones indicated by the combined data. The user-programmable clock is also responsive to the keyboard to sequentially route identical data which is entered from the keyboard to a plurality of memory locations in the first tier of the event memory wherein the addresses of the memory locations correspond to successive minutes of time. Means are provided for adjusting the duration of the function execution for each event identified by each memory location of the first tier of memory. By adjusting the duration of the execution to a time period equal to the time increment of each memory location of the first tier, a function may be executed for a time period which exceeds the time increment represented by each of the memory locations of the first tier.

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