H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/138
H01L 21/60 (2006.01) H01L 21/768 (2006.01)
Patent
CA 1282873
ABSTRACT OF THE DISCLOSURE A method is disclosed for fabricating a VLSI MOS integrated circuit in which a first dielectric layer, a thin silicon layer, and then a second dielectric layer are deposited on the upper surface of a substrate. A trench is formed in the upper, second dielectric layer leaving a thin layer of the second dielectric layer overlying the thin silicon layer. A contact hole is then etched through the central part of the thin layer of the second dielectric layer, the thin silicon layer and the first dielectric layer to the surface of the substrate. Using the remaining outer portion of the thin layer of the dielectric layer as a mask over the underlying portion of the thin silicon layer, metal is selectively deposited into the contact hole. The remaining portion of the thin layer of the second dielectric layer is then removed and the trench is selectively filled with a metal that is in electrical contact with the metal filling the contact hole.
579221
Smart & Biggar
Standard Microsystems Corporation
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