Cmos circuit having a reduced tendency to latch

Details Cmos circuit having a reduced tendency to latch Cmos circuit having a reduced tendency to latch

H - Electricity

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H01L 29/16 (2006.01) H01L 21/265 (2006.01) H01L 27/092 (2006.01) H01L 29/08 (2006.01) H01L 29/167 (2006.01)

Patent

CA 1226965

ABSTRACT The tendency of a CMOS circuit to latch up is reduced by implanting ions of germanium or tin into the source and drain regions of the circuit. The low energy gap of these ions lowers the band gap of the source and drain regions, which in turn inhi- bits their ability to inject tarriers into the substrate and well.

490092

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