Method and device to execute two instruction sequences in an...

G - Physics – 06 – F

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354/230.71

G06F 9/30 (2006.01) G06F 9/312 (2006.01) G06F 9/38 (2006.01)

Patent

CA 1289670

ABSTRACT OF THE DISCLOSURE A data processing system executes two instruction sequences in an order determined in advance. The executions include selection of read/write instructions containing read/ write addresses. With the aid of the instructions a main memory common to both sequences is activated for data information read- ing/writing. During execution of the sequence which is second due to the order, data information is used which is not guaran- teed in advance as being independent of the data information obtained during execution of the sequence which is first due to the order. Increased data handling capacity is achieved in the following manner: both sequences are executed in parallel to start with. During execution of the first sequence the main mem- ory is prevented from being activated for writing due to the sec- ond sequence write instructions. A write address and data infor- mation included in a write instruction associated with the second sequence are intermediate-stored. The intermediate stored write address is compared with the read addresses of the second sequence, and data information is prevented from being read from the main memory upon likeness in addresses, the intermediate- stored data information being read instead. An address included in a read instruction associated with the second sequence is intermediate stored if this address has not been previosuly selected in conjunction with a write instruction associated with the second sequence. The intermediate-stored read address is compared with the write address of the first sequence and execu- tion of the second sequence is restarted upon likeness in addresses. When the first sequence has been finally executed, the intermediate-stored data information is transferred with the aid of the intermediate stored write address to the main memory.

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