Speed/power scaling for mos circuit

Details Speed/power scaling for mos circuit Speed/power scaling for mos circuit

H - Electricity

01

L

356/128, 356/149

H01L 27/02 (2006.01) H01L 27/088 (2006.01) H01L 27/112 (2006.01) H01L 29/10 (2006.01) H01L 29/76 (2006.01) H01L 29/78 (2006.01)

Patent

CA 1211230

ABSTRACT The power consumption and corresponding speed of an integrated circuit is scaled by means of adjusting the channel width for MOS transistors. A transistor is initially fabricated with a channel having a relatively large width. The channel receives a depletion type implant to make the transistor lightly depleted. An enhancement implant is applied to the channel to cover a selected area. The enhancement implant is made substantially stronger than the depletion implant. This results in a first section of the channel having a large threshold voltage while the second section of the channel has a relatively small pinch-off voltage. The size of the second section is selectively con- trolled to scale the source-drain current of the transistor and the correspond- ing power consumption of the transistor. The method of applying the first and second implants can be easily incorporated into conventional ROM fabrication without the need for additional manufacturing steps.

418514

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