Method for manufacturing vlsi complementary mos-field effect...

Details Method for manufacturing vlsi complementary mos-field effect... Method for manufacturing vlsi complementary mos-field effect...

H - Electricity

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356/128

H01L 21/82 (2006.01) H01L 21/265 (2006.01) H01L 21/8238 (2006.01)

Patent

CA 1211865

ABSTRACT OF THE DISCLOSURE A method for manufacturing a CMOS circuit wherein a process sequence matched to an n-tub manufacture is carried out. Short-channel properties of n-channel transistors are improved by performing double boron implantations of the channel regions. A shared channel implantation is executed for both transistor types. Compared to traditional CMOS processes in n-tub structure, this eliminates involved masking steps. Also, the polysilicon gate is shielded from the boron ion implantation by means of a masking re-oxidation step and the under-diffusion given n-channel an p-channel transistors is greatly reduced by means of pull-back of the boron source/drain implantation. This contributes significantly to a symmetrical UT behavior of the transistors and to the attainment of high switching speeds. The method is used in the manufacture of VLSI CMOS circuits in VLSI technology.

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