Elastic memory with arrangement for reducing phase...

Details Elastic memory with arrangement for reducing phase... Elastic memory with arrangement for reducing phase...

G - Physics

06

F

354/231

G06F 1/04 (2006.01) G06F 5/06 (2006.01) H04J 3/07 (2006.01)

Patent

CA 1181527

ABSTRACT OF THE DISCLOSURE An arrangement for reducing phase fluctuations in the output or reading clock pulse of elastic memories which are produced during the absence and return of the external input clock pulse. According to the invention, the writing and reading clock pulses are replaced immediately upon the absence of the external input clock pulse by a clock pulse generated at the desired frequency fo so that the minimum distance between the written-in memory cell and the read-out memory cell remains in effect even for the time of the operating malfunction and no additional regulating processes are required when the external input clock pulse reappears.

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