Method and apparatus for predicting valid performance of...

Details Method and apparatus for predicting valid performance of... Method and apparatus for predicting valid performance of...

G - Physics

06

F

354/133, 354/149

G06F 12/10 (2006.01)

Patent

CA 1313269

- 40 - A METHOD AND APPARATUS FOR PREDICTING VALID PERFORMANCE OF VIRTUAL-ADDRESS TO PHYSICAL-ADDRESS TANSLATIONS Abstract A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performace of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.

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