H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/149
H01L 29/76 (2006.01) H01L 21/306 (2006.01) H01L 21/76 (2006.01) H01L 21/8252 (2006.01) H01L 27/06 (2006.01) H01L 29/778 (2006.01) H01L 29/80 (2006.01) H01L 27/088 (2006.01) H01L 27/095 (2006.01)
Patent
CA 1214575
A METHOD OF MANUFACTURING GaAs SEMICONDUCTOR DEVICE ABSTRACT OF THE DISCLOSURE Amethod of manufacturing a GaAs semiconductor device of an E/D construction having a GaAs/AlGaAS heterojunction and utilizing two-dimensional electron gas, comprising the steps of forming a heterojunction semiconductor substrate and etching a portion of the substrate to provide a gate portion of a depletion-mode FET. When the substrate comprising a semi-insulating GaAs layer, an undoped GaAs, an N-type AlGaAs layer of an electron-supply layer, and a GaAs layer is formed, the GaAs layer is composed of a first GaAs layer, an etching stoppable AlGaAs layer, and a second GaAs layer, the first GaAs layer being formed on the N type GaAs layer. The etching for provision of the gate portion is carried out by a dry etching method using an etchant of CCl2F2 gas, so that the second GaAs layer can be etched but the AlGaAs layer cannot be etched. Thus, the thickness of the layers between a gate electrode of the depletion-mode FET and the GaAs/AlGaAs heterojunction plane is determined at the formation of the hetero- junction substrate, consequently a better uniformity of the threshold voltage of depletion-mode FET's is obtained.
449399
Fujitsu Limited
Mcfadden Fincham
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