Circuit for decoding a diphase signal

Details Circuit for decoding a diphase signal Circuit for decoding a diphase signal

G - Physics

11

B

354/67

G11B 20/14 (2006.01)

Patent

CA 1169152

- 1 - ABSTRACT Incoming diphase signals E which have base bit intervals delineated by spaced clocking signals with data information occurring between the clocking signals are fed to a four bit shift register 10 which in cooperation with an exclusive OR-gate 14 generates a pulse D for each diphase signal E transition. Upon receipt of a preamble comprising four diphase signal transitions, a shift register 16 pro- vides a signal MSR which initiates the decoding of the following data information. A counter 24 stores counts related to the time intervals between each two successive clocking signals and counters 26 and 28 store a count related to an immediately subsequent time period which is three-fourths of the time interval. The occurrence of data information is sensed by a logic array 20 during successive time periods and a non- return to zero mark-space output signal K is stored in a flip-flop 22. The logic array 20 continually updates the mounts stored by the counters 24, 26-28. Thomas 2

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