Depletion mode fet logic system

Details Depletion mode fet logic system Depletion mode fet logic system

H - Electricity

03

K

328/128

H03K 19/017 (2006.01) H01L 27/08 (2006.01) H01L 29/80 (2006.01) H03K 19/00 (2006.01) H03K 19/094 (2006.01)

Patent

CA 1244529

DEPLETION MODE FET LOGIC SYSTEM Abstract of the Disclosure A GaAs D-MESFET logic system having a low power delay product has a switching section and a voltage level shifting section. The voltage level shifting section consists of a chain of diodes and a pulldown transistor. The switching section consists of an array of D-MESFETs which acts to speed up operation of a coupling capacitor. The low power dissipation of known capacitor coupled D-MESFET logic is thus preserved, while reducing gate delay. 12

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