Method of fabricating a tapered via hole in polyimide

Details Method of fabricating a tapered via hole in polyimide Method of fabricating a tapered via hole in polyimide

H - Electricity

01

L

356/134, 96/256

H01L 21/312 (2006.01) H01L 21/311 (2006.01) H01L 21/768 (2006.01)

Patent

CA 1266724

ABSTRACT OF THE DISCLOSURE METHOD OF FABRICATING A TAPERED VIA HOLE IN POLYIMIDE A method of fabricating a tapered via hole in a polyimide layer of an integrated circuit includes the steps of disposing a layer of SiO2 on the polyimide layer and a layer of photoresist on the SiO2 such that the layers have an opening which exposes a region of the polyimide layer for the via hole; etching the exposed polyimide region partway through the polyimide layer, while simultaneously etching back the photoresist on the sidewalls of the opening to thereby uncover a strip of SiO2 adjacent to the perimeter of the exposed polyimide region; enlarging the exposed region of the polyimide by etching the uncovered strip of SiO2; and repeating the etching step and enlarging step a predetermined number of times.

518649

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