Cmos integrated circuit having a top-side substrate contact...

Details Cmos integrated circuit having a top-side substrate contact... Cmos integrated circuit having a top-side substrate contact...

H - Electricity

01

L

356/141

H01L 21/74 (2006.01)

Patent

CA 1315020

69904-126 ABSTRACT OF THE DISCLOSURE A new and improved CMOS fabrication process provides a device having a low resistance top-side connection to its substrate. A high-resistivity epitaxial layer is applied to a low-resistivity substrate. Subsequently, a region of highly con- centrated impurities is introduced around the periphery of the epitaxial layer. Once this high-concentration region is in place and before any active components are formed, the region is heated under controlled conditions such that the impurities diffuse downwardly through the epitaxial layer until they contact the low-resistivity substrate. As a result, a top-side connection to the substrate is created which has a significantly reduced resistance. The top-side connection is compatible with TAB packaging processes and the reduced resistance of the connection enhances the device's immunity to latch-up. ' . .

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