Semiconductor planarization process and structures made thereby

Details Semiconductor planarization process and structures made thereby Semiconductor planarization process and structures made thereby

H - Electricity

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356/141

H01L 21/762 (2006.01) H01L 21/3105 (2006.01) H01L 21/311 (2006.01) H01L 21/316 (2006.01)

Patent

CA 1232368

ABSTRACT A silicon substrate having a silicon dioxide bird's head is provided. A thermal oxide layer is grown on the exposed silicon surface. A layer, e.g., 4000 A°, of phosphogermanosilicate glass is deposited on the thermal oxide and on the silicon dioxide bird's head. The structure is heated to 950°C, causing a reflow of the glass which results in a planar surface. The thermal oxide and the phosphogemanosilicate glass are then wet etched at the same rate with a solution of hydrofluoric acid, ammonium fluoride, and deionized water. The wet etch is terminated when the exposed silicon surface is reached, resulting in a smooth surface as defined by the planar reflow surface. Other embodiments are disclosed.

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