Redundant rows in integrated circuit memories

Details Redundant rows in integrated circuit memories Redundant rows in integrated circuit memories

G - Physics

06

F

354/224, 352/41

G06F 11/20 (2006.01) G11C 11/40 (2006.01) G11C 29/00 (2006.01)

Patent

CA 1215471

REDUNDANT ROWS IN INTEGRATED CIRCUIT MEMORIES Abstract of the disclosure Decoding apparatus for an integrated circuit memory having normal rows of memory cells and at least one selectively connectable redundant second row of memory cells for being connected in place of one of the first rows, said apparatus including: a redundant decoder connected to each of the at least one redundant row, the redundant decoder including a plurality of selectable connections for creating an address for each of the at least one redundant row; a control signal generating circuit for generating a control signal of a first state until an address is supplied to the memory and of a second state if any of the at least one redundant row is selected by the address; and, another decoder connected to receive the control signal from the generating circuit for controlling the normal rows in response thereto.

445251

Affiliated with

Also associated with

Rating

Redundant rows in integrated circuit memories does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Redundant rows in integrated circuit memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundant rows in integrated circuit memories will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1213590