G - Physics – 06 – F
Patent
G - Physics
06
F
354/241
G06F 12/08 (2006.01)
Patent
CA 1269176
ABSTRACT A microprocessor system architecture is disclosed having a high-speed system bus for coupling system elements coupled thereto for high-speed communica- tions thereamong, and having a dual bus microprocessor having separate ultra-high speed instruction and data cache interfaces coupled to independently operable instruction and data caches, respectively. The caches are coupled to the system bus as well as to the micro- processor. A primary main memory is coupled to the system bus for selectively storing and outputting digital information. The instruction and data caches are coupled to the primary memory via the system bus for indepen- dently and selectively managing and accessing the primary memory for selectively storing and outputting digital information to respective mapped addressable very high- speed cache memory. The system bus provides a high-speed bus coupled to the primary memory, instruction cache, and data cache, and other system elements, for communicating the information therebetween at a high rate. The micro- processor is coupled via separate and independent very high-speed instruction and data buses to each of the instruction cache and data cache, respectively, for processing data received from the data cache responsive to instructions received from the instruction cache. The instruction bus and data bus are exclusive and indepen- dent of one another. This provides for very high speed instruction transfer from the instruction cache to the microprocessor via the instruction bus and allows for simultaneous very high-speed transfer of data between the data cache and the microprocessor via the data bus. The data cache and instruction cache each have separate dedicated system bus interfaces for coupling to the main memory and to other peripheral devices which are coupled to the system bus. Numerous other system elements can also be coupled to the system bus, including an interrupt controller, an I/O processor, a bus arbiter, an array processor, and other peripheral controller devices.
502415
Cho James Youngsae
Hollingsworth Walter H.
Sachs Howard Gene
Fairchild Camera And Instrument Corporation
Smart & Biggar
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