Method of and apparatus for frame decoding

Details Method of and apparatus for frame decoding Method of and apparatus for frame decoding

H - Electricity

04

J

363/17

H04J 3/06 (2006.01)

Patent

CA 1267239

ABSTRACT METHOD OF AND APPARATUS FOR FRAME DECODING In a method of and apparatus for frame decoding, in particular in a multiplexer-demultiplexer system for digital signal transmission, in which a series bit flow (BS) has a frame structure including a periodically occurring item of synchronising information which characterises the start of each frame, a synchronising bit (S) is used as synchronising information. Commencing with the m-th search frame, and the following (m+1)-th search frame - where each search frame has the same number of bits as the frame - a logic AND-link is performed, where the result provides the (m+1)-th search frame for the next logic-link. It is determined when only one bit, the synchronising bit, in the search frame is set at logic "1" and this setting is retained for a plurality of search frames. A synchronising signal (SS) corresponding to the time position of the synchronising hit is generated and the bit flow and/or the synchronising signal are delayed in such manner that the synchronising signal and the synchronising bit occur in synchronism.

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