Multiplexer/demultiplexer circuitry for lsi implementation

Details Multiplexer/demultiplexer circuitry for lsi implementation Multiplexer/demultiplexer circuitry for lsi implementation

H - Electricity

04

J

344/25

H04J 3/06 (2006.01) H04Q 11/06 (2006.01)

Patent

CA 1297568

NE-116-MK (099A/2) "Multiplexer/Demultiplexer Circuitry for LSI Implementation" ABSTRACT OF THE DISCLOSURE A multiplexer/demultiplexer comprises a code pattern generator for generating a series of unique code patterns at periodic intervals, a plurality of multiplexers cascaded from the code pattern generator to one end of a channel. Each of the multiplexers includes a synchronizer for detecting a particular one of the unique code patterns and a slot selector for multiplexing input data packets into time slots uniquely identified by the particular code pattern to form a data bit stream with the code patterns which is forwarded to the channel. A plurality of demultiplexers are connected to the opposite end of the channel, each of the demultiplexers comprising a synchronizer for detecting a particular one of the code patterns from the data bit stream and a gate for extracting data packets from the time slots uniquely identified by the detected code pattern.

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