G - Physics – 06 – F
Patent
G - Physics
06
F
354/243
G06F 9/46 (2006.01) G06F 13/42 (2006.01)
Patent
CA 1304167
METHOD AND APPARATUS FOR MANAGING MULTIPLE LOCK INDICATORS IN A MULTIPROCESSOR COMPUTER SYSTEM Abstract A computer system having multiple processors inter- connected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O node. Acknowledge con- firmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processes in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the mem- ory which indicates that the specified location is locked.
565473
Gillett Richard B. Jr.
Williams Douglas D.
Digital Equipment Corporation
Smart & Biggar
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