H - Electricity – 04 – L
Patent
H - Electricity
04
L
328/28
H04L 7/02 (2006.01)
Patent
CA 1268523
Abstract of the Disclosure In a synchronization circuit for use in demodulating an input signal carrying a transmission data signal at a symbol rate, a sampling circuit samples the input signal at a predetermined sample rate which may be different from the symbol rate, to produce a sequence of sampled signals. The sampled signal sequence is interpolated by the use of an interpolator into first and second partial interpolated signals which have different phases from each other. The first and second partial interpolated signals are processed by a processing circuit to produce timing errors between the first partial interpolated signals and the sampled signal sequence. The processing circuit controls the phases of the first and second partial interpolated signals with reference to the timing errors so that both of the partial interpolated signals are derived at predetermined points of the sampled signal sequence. On reception of the transmission data signal of a multi-level divisible into a plurality of bits, the interpolator comprises a plurality of elementary interpolators for interpolating the respective hits to produce fragmentary interpolated signals. The fragmentary interpolated signals are combined into the interpolated signal sequence. The elementary interpolators may be controlled by two internal samplers in consideration of the timing errors.
494216
Corporation Nec
Smart & Biggar
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