Method of decoding binary signals and viterbi decoder as...

Details Method of decoding binary signals and viterbi decoder as... Method of decoding binary signals and viterbi decoder as...

G - Physics

06

F

354/68

G06F 11/10 (2006.01) H03M 13/41 (2006.01)

Patent

CA 1260615

ABSTRACT OF THE DISCLOSURE A method and circuit for decoding binary signals processed according to an error correcting convolution code, in which the path metrics are transformed from the arithmetic into the logic range of operation. The path metric having the extreme value is subtracted from all other path metrics. All possible binary signal states occurring at the encoder are simulated in real time and are utilized to address hypothetical source data channels. From such a hypothetical source data channel fed by path decision bits, a buffer memory is actualized as well as the simulated binary signal states at the encoder. The output of decoded data from a buffer memory is effected in accordance with their addresses, namely for the extreme value of the path metric. For branching in the trellis diagram, the buffer memories whose associated trellis paths did not survive are overwritten. - ? -

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