Logic path length reduction using boolean minimization

Details Logic path length reduction using boolean minimization Logic path length reduction using boolean minimization

G - Physics

06

F

354/120

G06F 17/50 (2006.01)

Patent

CA 1287174

Abstract of the Disclosure An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.

580777

Affiliated with

Also associated with

Rating

Logic path length reduction using boolean minimization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic path length reduction using boolean minimization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic path length reduction using boolean minimization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1227527