G - Physics – 06 – F
Patent
G - Physics
06
F
354/231
G06F 13/40 (2006.01) G06F 5/06 (2006.01) G06F 13/42 (2006.01)
Patent
CA 1305560
ABSTRACT A bus adapter connecting a high-speed pended bus to a slower speed non-pended bus includes a first module functioning as a node of the pended bus and a second module functioning as a node of the non-pended bus. An interconnect bus extends between the two modules. Control signals on the interconnect bus generated by the first module comprise status signals having an indefinite assertion duration, and are deasserted only in response to con- trol signals on the interconnect bus generated by the second module, which have a finite duration. Control signals on the interconnect bus generated by the first module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non- pended bus. Control signals on the interconnect bus generated by the second module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.
576396
Bloom Elbert
Hartwell David W.
Triolo Victoria M.
Digital Equipment Corporation
Smart & Biggar
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