Flip-flop in imbedded test system for vlsi

Details Flip-flop in imbedded test system for vlsi Flip-flop in imbedded test system for vlsi

G - Physics

01

R

328/150, 324/58.

G01R 31/28 (2006.01) G01R 31/3185 (2006.01) G06F 11/26 (2006.01)

Patent

CA 1259671

ABSTRACT OF THE DISCLOSURE A logic chip contains a plurality of ranks of flip-flops with combinational logic elements connected in between the flip-flop ranks. Each flip-flop has at least two distinct data paths. The first path is for the normal passage of data to combinational logic units following the rank of flip-flops, and the second path is a test path which is connected directly with the next rank of flip-flops. Operands may be shifted in parallel to bypass combinational logic units and may be directed to selected combinational logic for test purposes. The flip-flops in a rank may be serially scanned or operate in parallel to send specific operands through selected combinational logic units.

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