Method of fabricating integrated circuit structures using...

Details Method of fabricating integrated circuit structures using... Method of fabricating integrated circuit structures using...

H - Electricity

05

K

149/10

H05K 3/06 (2006.01) H01L 21/033 (2006.01) H01L 29/732 (2006.01)

Patent

CA 1223800

A METHOD OF FABRICATING INTEGRATED CIRCUIT STRUCTURE USING REPLICA PATTERNING ABSTRACT OF THE DISCLOSURE A method of defining narrow regions in an underlying integrated circuit structure includes the steps of depositing a first layer of material 12 having selected etching characteristics on the underlying integrated circuit structure, depositing a second layer of material 13 having etching characteristics different from the first layer 12 on the first layer 12, anisotropically etching the first layer 12 and the second layer 13 from all of the underlying integrated circuit structure 10 except for a desired region having a periphery which includes the narrow region, forming a coating 15 of smoothing material over all of the underlying integrated circuit structure 10 except for the first layer 12, and isotropically etching the first layer 12 to remove it from the surface of the underlying integrated circuit structure 10 to thereby define the narrow region. Use of the process to fabricate a compact bipolar transistor structure is also disclosed.

453211

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