Static memory cell embodying dual-channel technology

Details Static memory cell embodying dual-channel technology Static memory cell embodying dual-channel technology

G - Physics

11

C

352/82

G11C 11/40 (2006.01) G11C 11/412 (2006.01) H01L 27/11 (2006.01)

Patent

CA 1208364

ABSTRACT OF THE DISCLOSURE A static memory cell has two switching transistors of a first channel type disposed on a semiconductor substrate which are connected through respective load elements of a second channel type to a supply voltage, the drain terminals of the switching transistors being cross-connected to the gate of the other transistor as well as to the gate of the load element connected in series therewith. Each of the load elements consists of highly doped sections of a layer of polycrystalline silicon covering the substrate with an insulating layer therebetween and weakly or non-doped portions of the polycrystalline silicon layer forming a channel region between the highly doped sections. An additionally doped region of the semiconductor substrate functioning as a gate region is disposed below the channel region. This construction substantially reduces the surface area of the substrate occupied by the memory cell.

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