Method for zero byte time slot interchange

Details Method for zero byte time slot interchange Method for zero byte time slot interchange

H - Electricity

04

Q

344/1

H04Q 1/20 (2006.01) H04J 3/04 (2006.01) H04L 7/00 (2006.01)

Patent

CA 1281107

A METHOD FOR ZERO BYTE TIME SLOT INTERCHANGE ABSTRACT OF THE INVENTION This method is a scheme for suppressing excessive amounts of logic zeros transmitted via T-carrier line facilities between switching systems or channel banks. This scheme provides proper zero bit suppression for alternating mark inversion signalling (AMI). A proper AMI signal contains no more then 15 consecutive logic zero bit positions. In addition, a proper AMI signal should contain a logic 1 density of an average of one logic 1 per 8-bits of information over every consecutive 3 octet group. This scheme provides for encoding and decoding a 4 frame octet group of an extended superframe. Logic ones are introduced into octets which would otherwise violate the AMI signalling rules. These logic ones are then removed by the receiving system and replaced with the indicated all zero octets before being given to down stream processing.

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