G - Physics – 06 – F
Patent
G - Physics
06
F
354/204
G06F 7/544 (2006.01)
Patent
CA 1257003
Abstract of the Disclosure: An arithmetic circuit comprises a first subtracter receiving first and second input signals which are composed of a plurality of bits and operative to output a first output signal representative of the first input signal minus the second input signal, and a second subtracter receiving the first and second input signals so as to output a second output signal representative of the second input signal minus the first input signal. A selector receives the first and second output signals and operates in response to one of the first and second output signals so as to alternately output the first and second output signals.
511963
Enomoto Tadayoshi
Yamashina Masakazu
Yasumoto Masaaki
Corporation Nec
Smart & Biggar
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