Method and apparatus for simulating memory arrays in a logic...

Details Method and apparatus for simulating memory arrays in a logic... Method and apparatus for simulating memory arrays in a logic...

G - Physics

06

F

354/1

G06F 17/50 (2006.01) G06F 11/26 (2006.01)

Patent

CA 1256563

METHOD AND APPARATUS FOR SIMULATING MEMORY ARRAYS IN A LOGIC SIMULATION MACHINE ABSTRACT OF THE DISCLOSURE A method and apparatus for simulating memory devices in a logic simulation machine. Both include a finite state machine (FSM) having input/output (I/O) sources, instruction storage resources, a real memory resource, and instruction execution resources. A plurality of memory device ports to be simulated are defined and associated with corresponding respective subsets of the I/O resources of the FSM. Permutated sets of simulated memory array access signals, such as data, address, and control, are bound to selectable ones of the simulated memory ports and stored in the FSM, with the parameters of the memory operation established by the simulated signals. Stored sets of access instructions, representative of memory access operations, are augmented by the simulated signals and executed by the FSM against the real memory resource. All array instructions representing the same memory array share the same address space in the real memory resource.

530789

Affiliated with

Also associated with

Rating

Method and apparatus for simulating memory arrays in a logic... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for simulating memory arrays in a logic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for simulating memory arrays in a logic... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1241938