Dual bus system

Details Dual bus system Dual bus system

G - Physics

06

G

354/232

G06G 7/48 (2006.01) G06F 13/28 (2006.01)

Patent

CA 1252573

Abstract of the Invention The data processing system, has at least one memory unit operatively connected to a memory bus, and further has an input/output (I/O) bus controller for interfacing at least one peripheral device to the data processing system. The data processing system comprises a first bus which provides a first transmission medium between the peripheral device and the memory bus. A second bus, provides a second transmission medium between a CPU and the memory bus. A logic element, interposed between the first and second bus, and the memory bus, interfaces the first and second bus to the memory bus in response to request signals from the first and second bus.

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