Method of building a variety of complex integrated circuits...

Details Method of building a variety of complex integrated circuits... Method of building a variety of complex integrated circuits...

H - Electricity

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H01L 23/48 (2006.01) G01R 31/3185 (2006.01) G11C 29/00 (2006.01) H01L 23/13 (2006.01) H01L 23/473 (2006.01) H01L 23/52 (2006.01) H01L 23/538 (2006.01) H05K 3/34 (2006.01) H05K 7/20 (2006.01) H05K 1/00 (2006.01) H05K 1/14 (2006.01) H05K 3/40 (2006.01)

Patent

CA 1319203

ABSTRACT A novel packaging system for VLSI circuits allows low-cost construction and maintenance of complex high density high- performance devices with low power requirements. The devices can be individually created by software means from a small selection of standardizable IC chips by disposing a plurality of chips in leadless chip carriers in a mosaic on a substrate, and configuring them by software to selectively communicate with other chips of the mosaic or even to individually change their operating function. The immediate juxtaposition of the chip carriers in the mosaic eliminates transmission line data skew, and also allows considerable savings in chip space and power requirements by dispensing with interconnection drivers, receivers and bonding pads. The chip carrier mosaics may be assembled into modules suitable for plug-in connection to an interconnecting backplane to create even larger devices, and individual modules can be dynamically tested in their high-performance mode by configuring one or more modules as test modules and either plugging them into modules to be tested or making them a permanent part of the device's module array.

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