Bus transmitter having controlled trapezoidal slew rate

H - Electricity – 03 – K

Patent

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328/95

H03K 19/094 (2006.01) H03K 4/94 (2006.01) H03K 17/16 (2006.01) H03K 19/003 (2006.01) H03K 19/0948 (2006.01)

Patent

CA 1292521

ABSTRACT OF THE DISCLOSURE A transmitter circuit for transmitting a digital data signal over a bus in a digital data processing system includes a MOSFET bus driver transistor having a gate to drain capacitance CGD which substantially dominates other capacitances at the gate terminal. The bus driver transistor is driven by a buffer circuit having pull-up and pull-down transistors current through which is controlled by current sources. The gate terminal of the driver transistor is connected to, and controlled by, the node between the pull-up and pull-down transistors. The drain terminal of the driver transistor is connected to, and controls, a bus line. To assert a signal on the bus line, the pull-up transistor is turned on to drive current into the node at a rate governed by the current source, which increases the voltage level of the node. When the voltage level of the node reaches the driver transistor's threshold level, the driver transistor begins to turn on, allowing the voltage level of the bus line to drop. Contemporaneously, current flows into the node from the bus line through the driver transistor's high gate to drain capacitance, thereby limiting the voltage level of the node, and thus the current flow through the driver transistor. Thus, current flows through the driver transistor from the bus line in a manner controlled, in part, by the voltage level on the bus line. In negating a signal on the bus line, the operations are similar, with current flowing out of the node through the pull-down transistor and the driver transistor's gate to drain capacitance.

566114

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