G - Physics – 06 – F
Patent
G - Physics
06
F
354/236
G06F 13/12 (2006.01)
Patent
CA 1324838
27 Abstract of the Disclosure: In a data processing system having a data path (30) between a memory device (11) and input-output devices (12), and a holding device (18) for holding first through N-th firmware data, where N represents an integer greater than one, an input-output processor (13) comprises first through N-th control memory layers of control memories (31, 32, 33) and a data controller (34) connected to the holding device. Responsive to a firmware load instruction (23), the data controller reads the first through the N-th firmware data from the holding device as first through N-th read-out data. The holding device makes the memory device memorize the first through the N-th read-out data as first through N-th memorized data. Connected to the control memories, the data controller makes the control memories of the first through the N-th control memory layers memorize the first through the N-th memorized data through the data path. In this event, the data controller makes at least one control memory of each of the first through the N-th control memory layers simultaneously memorize each of the first through the N-th memorize data. The holding device may be included in one of the input-output devices. The firmware data may be stored in the control memories successively from the first control memory layer to the N-th control memory layer. Alternatively, storage of the firmware data may be made from the N-th control memory layer to the first control memory layer.
609922
Fukuta Toru
Oyadomari Hajime
Corporation Nec
Smart & Biggar
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