G - Physics – 06 – F
Patent
G - Physics
06
F
354/235, 354/230
G06F 9/46 (2006.01)
Patent
CA 1173167
ABSTRACT A modulator terminal employs a CPU module connected via a bus to at least one slave module. An error condition is detected if a slave module fails to respond to a command by generating an operation acknowledge signal within a predetermined period of time associated with the time requir- ed for the slave module to execute the command. A memory mapping device is utilized to decode CPU address signals and generate related signals on a greater number of output lines coupled to the system bus thereby increasing the number of addressable locations otherwise accessible by the CPU. Im- proved prioritized bus communication is provided by way of a vectored inter- rupt scheme in which a priority line is coupled in a daisy chain fashion to other slave modules in the system. In the preferred embodiment the system employs distributed CPU modules employing an interprocessor interrupt tech- nique utilizing a pair of commonly accessible storage devices. One of the processors may be used as an emulator and a programmable logic array is advantageously utilized in the emulator processor.
434741
Nixdorf Computer Corporation (the)
Smart & Biggar
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