Constraint application processor

Details Constraint application processor Constraint application processor

G - Physics

01

S

349/25, 343/67

G01S 7/02 (2006.01) G01S 7/54 (2006.01) H01Q 3/26 (2006.01)

Patent

CA 1231423

ABSTRACT A constraint application processor is arranged to apply a linear constraint to signals from antennas. A main antenna signal is fed to constraint element multipliers and thence to respective adders for subtraction from subsidiary antenna signals. Delay units delay the subsidiary signals by one clock cycle prior to subtraction. The main signal is also fed via a one cycle delay unit to a multiplier for amplification by a gain factor. Main and subsidiary outputs of the processor may be connected to an output processor for signal minimisa- tion subject to the main gain factor remaining constant. The output processor may be arranged to produce recursive signal residuals in accordance with the Widrow LMS algorithm. This requires a processor arranged to sum main and weighted subsidiary signals, weight factors being derived from preceding data, residual and weight factors. Alternatively, a systolic array of processing cells may be employed.

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