Digital signal processor architecture

G - Physics – 06 – F

Patent

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354/166

G06F 15/00 (2006.01) G06F 15/78 (2006.01)

Patent

CA 1292073

ABSTRACT OF THE DISCLOSURE A digital signal processor (DSP) for conducting arithmetically complex functions, is provided. The DSP generally comprises a microinstruction sequencer (MIS) section, an arithmetic logic unit (ALU), a serial arithmetic processor section, a RAM section, and a system data bus. The MIS includes a coded ROM, means for addressing the ROM, means for decoding the ROM code into control and data signals, and means for sending the control and data signals to desired locations, and controls the functioning of the DSP. The ALU performs arithmetic and logic functions under the control of the ROM, while the serial arithmetic processor section conducts arithmetically complex functions under the control of the ROM. The RAM, under control of the ROM receives and stores data which is sent to the RAM via a system data bus directly from the ROM, from the ALU, from the serial arithmetic processor, and from circuitry exterior to the DSP. The RAM also sends via the data bus data to the ALU, the serial arithmetic processor, the microinstruction sequencer and the circuitry exterior to said digital signal processor under control of the ROM. The provided DSP is particularly advantageous in carrying out ADPCM algorithms.

571059

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