Non-pll concurrent carrier clock synchronization

H - Electricity – 04 – L

Patent

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325/111

H04L 7/02 (2006.01) H04L 7/027 (2006.01) H04L 27/22 (2006.01) H04L 27/227 (2006.01)

Patent

CA 1198170

NON-PLL CONCURRENT CARRIER CLOCK SYNCHRONIZATION ABSTRACT Concurrent carrier and clock synchronization are derived from an input signal in interdependent loops without the use of phase look loop (PLL) circuitry in order to improve operation at higher bit rates. An acquisition detection signal is generated only in response to predetermined minimum errors in both the received signal amplitude and the recovered carrier phase.

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