Multiprocessor level change synchronization apparatus

Details Multiprocessor level change synchronization apparatus Multiprocessor level change synchronization apparatus

Category

G - Physics

Subcategory

06

Subsubcategory

F

CPC

354/234

IPC codes

G06F 9/46 (2006.01) G06F 9/48 (2006.01) G06F 13/26 (2006.01)

Type

Patent

Patent number

CA 1286415

Description

ABSTRACT OF THE DISCLOSURE Apparatus is included within the bus interface circuits of each processing unit of a multiprocessing system which connect in common with the other units of the system to an asynchronous system bus. The apparatus and interrupt couples to the processing unit's level register and interrupt circuits. In response to a command specifying a level change, the apparatus conditions these circuits to store level and interrupt signals applied to the system bus as part of such CPU command during a bus cycle of operation granted to the processing unit on a priority basis. This ensures the reliable switching between interrupt levels and the notification of such level changes to the other units of the system without interference from other processing units.

Application Number

540644

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