Multiple channel depacketizer

Details Multiple channel depacketizer Multiple channel depacketizer

H - Electricity

04

Q

344/25

H04Q 11/04 (2006.01)

Patent

CA 1230402

MULTIPLE CHANNEL DEPACKETIZER Abstract of the Disclosure Asynchronous packets for a plurality of channels, each packet comprising a channel address and two information bytes, are stored in a FIFO. The address in the packet is used with a first pointer to address a RAM for storing the bytes therein. The RAM is cyclically addressed by a channel address together with a second pointer to read the bytes out synchronously to the relevant channel. Updating of the second pointer is inhibited for each channel initally to prime the RAM with bytes for the channel, and if the pointers become equal. The bytes may comprise speech samples or data. A mapped memory may be provided for converting between channel addresses in the packets and output channel addresses. - i -

471081

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